The integrated circuit (IC) industry is faced with the challenge of providing memory products, such as static random access memory (SRAM), dynamic random access memory (DRAM), embedded DRAM, nonvolatile memory, floating gate memory, and like memory devices, with higher storage capacities while simultaneously reducing power consumption and improving access speeds. FIG. 1 illustrates a modern memory architecture 10 which is commonly used in conventional, high density, low power, high speed, low cost SRAM ICs. In FIG. 1, the entire memory capacity is generally split into two memory arrays 12 and 14. To obtain greater speed*power performance, the device of FIG. 1 uses current sensing techniques.
Unlike conventional SRAM memory circuits which use voltage sensing, modern SRAM memory devices are now utilizing current sensing whereby data read from the memory arrays 12 and 14 are provided with improved speed*power performance. Therefore, the memory cells in the arrays 12 and 14 transport current through the current global data bus 18 and 20 whereby the magnitude of the current through current global data bus lines will determine the logic value that is stored in each memory cell that is subject to the read operation. For example, if a positive differential current flow is detected by any of the sense amplifier circuits 24-31, that value will be read as a logic 1. In the same manner, if a negative differential current is detected by any one of the sense amplifier circuits 24-31, a logic 0 is output for that selected memory device. The current global data buses, 16, 18, 20, and 22 provide this positive or negative differential current to current-to-voltage converters 24-31 in FIG. 1. The converters 24-31 convert the current (I) from the current global data buses 16-22 to differential voltage (V) signals which are provided to output circuits/drivers 35-42 in FIG. 1.
While current sensing provides improved performance in memory devices, current sensing is a new technology used in static random access memories (SRAMs). Since current sensing in SRAMs is new, current sensing presents many new and different challenges to the IC industry. As an example, customers are now requesting that the current sensing memory configurations of FIG. 1 be provided in one of two selectable word-size configurations. Specifically, customers are asking that the device of FIG. 1, which is a x36 word size product, be provided in a x18 word size as well.
The FIG. 1 illustrates a device which is hard-wired to provide only 36-bit wide data through thirty-six output terminals located external to the integrated circuit (IC). In FIG. 1, nine bits are provided via a right half of the array 12, nine bits are provided via a left half of the array 12, nine bits are provided from the right half of the array 14, and a final nine bits (for a total of thirty-six bits) are provided from the left half of array 14 as shown. Some customers may want a x18 data word mode in FIG. 1 where the word size of the device 10 is halved from x36 bits to x18 bits. In this case, instead of reading in parallel from both arrays 12 and 14 to provide 36 bits, only one of the arrays 12 or 14 needs to be accessed at any one point in time whereby only 18 bits are provided per access to the lowest order bits of the data bus output terminals. The x18 mode requires some architectural modifications in FIG. 1 so that the 18 bits are provided to the correct low order IC pins regardless of which array (array 12 or 14) they are read from.
In the prior art, when using the conventional SRAM voltage sensing scheme, a designer could easily change between a x18 and x36 configuration by simply electrically shorting the bus 16 to the bus 18 and by electrically shorting the bus 20 to the bus 22 with a little added tri-state logic. However, when using the current sensing scheme in modern SRAMs, the electrical shorting of the buses 16 and 18 and the electrical shorting of the buses 20 and 22 is not feasible. If one were to short these buses together, parasitic resistance and capacitance on the bus would result in a severe degradation in the reliability and performance of the current sensed product. The added resistance and capacitance would make accurate and consistent sensing of the cell current nearly impossible during read operations of the arrays 12 and 14. Therefore, prior art methods of converting a first memory configuration to a second memory configuration by bus short circuiting are not feasible in the modern current sensed SRAM devices.
Another method that may be used to provide two products of different word sizes is to design two separate integrated circuits, one for the first memory configuration and yet another for the second integrated circuit configuration. The costs, maintenance, design, upkeep, testing, manufacture, and shipping of two completely different integrated circuits is not an attractive solution. Maintaining two integrated circuits would add extra cost to the design, consume valuable engineering resources that could be used elsewhere, reduced time to market, and involve other disadvantages. Generally, it would be better to design one product that could be easily configured into either a x18 mode or a x36 mode without designing two totally separate product lines.
Therefore, a need exists in the industry for a memory architecture, which uses current sensing capability, that can be configured in one of many different word size modes of operation while maintaining the efficient speed*power product of the current sensing solution.